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Altera_Forum
Honored Contributor
Honored ContributorVHDL: inout port error: multiple drivers
Hello, I have defined an entity with some ports. One of these ports is defined as follows: data : inout std_logic_vector (63 downto 0); As you see, I want to read from or wr...
Altera_ForumHonored Contributor
Honored Contributora way round this, and a method that would more accuratly describe real hardware at an internal level (not at the pin-level) would be to have separate in and out ports. inout ports should only really be used at pin levels, and then they should be avoided if possible. You never need internal inout ports.
The problem should be showing up in simulation. If you drive 2 std_logics together and one of them isnt set to 'Z', you get 'X'. Any time you see 'X' appear in simulation you should investigate and fix the problem, as it usually means the exact problem you have.
