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Altera_Forum
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16 years ago

vhdl help

Hi, In vhdl can we make an pin declared as "inout" to act as input or as output depending on certain condition. entity rout is port( a : inout bit; b : inout bit; );...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

kaz, I have another problem want to share with you,and also with people visiting this website.That is I got a warning when I simulate my project in RTL using modelsim_altera.The warning is " There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." The wave was 'U',can't see their values.But when I try to simulate in GTL ,the values showed up.How to deal with this?