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Honored ContributorVHDL Help
Please help me to generate a clock in VHDL synchronised with rising edges of two external clocks.
External clocks are: 100Mhz and 124 Hz Clock to be generated: 10MHz The 10MHz clock is to be generated using 100MHz clock startin g from rising edge of 124Hz clock.22 Replies
Altera_ForumSorry, I read 124 as Mhz, not Hz.
Then yes, it should be ok, but it still doesnt really make sense unless you only want so many clock pulses - and then you might as well make it a clock enable. You would have to re-synchronise it every time you had a rising edge because it wouldnt be in sync by the time the 124Hz clock rose again.- Altera_Forum
hey can you provide some coding example for this requirement
- Altera_Forum
that is your job. I suggest you get coding, and come back here when you have problems.
- Altera_Forum
i hav already tried many logics...but not getting the right one...the newly generated 10MHz clock is not getting synchronized with 124Hz clock
- Altera_Forum
why not post some code, and we can tell you where you're going wrong.
- Altera_Forum
if clk_100'event and clk_100 = '1' then
if clk_124'event and clk_124 = '1' then if count <=10 then clk_10 = '1'; else clk_10 = '0'; end if; count = count + 1; if count > = 20 then count = 1; end if; end if; end if; - Altera_Forum
well theres a problem - you cannot try and read two clocks in 1 bit of code. Think about it - a register (that you are infering) cannot have two clock connections. You have to run the counter in one clock domain and then syncrhonise it into the other - or sample one clock in the other clock domain (and to do that you will need at least a 248Mhz clock to sample the 124Mhz clock properly).
- Altera_Forum
can i do like this:
process-1: if clk_100'event and clk_100 = '1' then if count <=10 then clk_10 = '1'; else clk_10 = '0'; end if; count = count + 1; if count > = 20 then count = 1; end if; end if; 2nd process: if clk_124'event and clk_124 = '1' then clk_10_new <= clk_10; endif; will this work? - Altera_Forum
here essentially i am generating required clock in process-1 and trying to sync it with 124Hz clock in process-2
- Altera_Forum
you could do that, but remember the 10Mhz clock is toggling at 10Mhz, so you dont know whether you'll sample a '1' or a '0' in the 124hz clock domain, so you may just get a load of zeros. Plus you have the potential for meta stability.
I suggest you sample the 124Hz clock in the 100 Mhz clock domain.
