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Honored Contributor
Honored ContributorVHDL Help
Please help me to generate a clock in VHDL synchronised with rising edges of two external clocks. External clocks are: 100Mhz and 124 Hz Clock to be generated: 10MHz The 10MHz clock is to be g...
Altera_ForumHonored Contributor
Honored ContributorSorry, I read 124 as Mhz, not Hz.
Then yes, it should be ok, but it still doesnt really make sense unless you only want so many clock pulses - and then you might as well make it a clock enable. You would have to re-synchronise it every time you had a rising edge because it wouldnt be in sync by the time the 124Hz clock rose again.
