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Honored Contributor
Honored ContributorVHDL Help
Please help me to generate a clock in VHDL synchronised with rising edges of two external clocks. External clocks are: 100Mhz and 124 Hz Clock to be generated: 10MHz The 10MHz clock is to be g...
Altera_ForumHonored Contributor
Honored Contributorcan i do like this:
process-1: if clk_100'event and clk_100 = '1' then if count <=10 then clk_10 = '1'; else clk_10 = '0'; end if; count = count + 1; if count > = 20 then count = 1; end if; end if; 2nd process: if clk_124'event and clk_124 = '1' then clk_10_new <= clk_10; endif; will this work?
