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Altera_Forum
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13 years ago

VHDL Help

Please help me to generate a clock in VHDL synchronised with rising edges of two external clocks. External clocks are: 100Mhz and 124 Hz Clock to be generated: 10MHz The 10MHz clock is to be g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

well theres a problem - you cannot try and read two clocks in 1 bit of code. Think about it - a register (that you are infering) cannot have two clock connections. You have to run the counter in one clock domain and then syncrhonise it into the other - or sample one clock in the other clock domain (and to do that you will need at least a 248Mhz clock to sample the 124Mhz clock properly).