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Altera_Forum
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13 years ago

VHDL Help

Please help me to generate a clock in VHDL synchronised with rising edges of two external clocks. External clocks are: 100Mhz and 124 Hz Clock to be generated: 10MHz The 10MHz clock is to be g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

you could do that, but remember the 10Mhz clock is toggling at 10Mhz, so you dont know whether you'll sample a '1' or a '0' in the 124hz clock domain, so you may just get a load of zeros. Plus you have the potential for meta stability.

I suggest you sample the 124Hz clock in the 100 Mhz clock domain.