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Honored ContributorVHDL Help
Please help me to generate a clock in VHDL synchronised with rising edges of two external clocks.
External clocks are: 100Mhz and 124 Hz Clock to be generated: 10MHz The 10MHz clock is to be generated using 100MHz clock startin g from rising edge of 124Hz clock.22 Replies
Altera_Forumhey can you provide some coding example for this requirement
- Altera_Forum
Sorry, I read 124 as Mhz, not Hz.
Then yes, it should be ok, but it still doesnt really make sense unless you only want so many clock pulses - and then you might as well make it a clock enable. You would have to re-synchronise it every time you had a rising edge because it wouldnt be in sync by the time the 124Hz clock rose again. - Altera_Forum
Actually i need to generate a clock for a sensor....i chose 100Mhz crystal for generating this clock on my pcb...but there is an external clock 124 Hz coming to the pcb and this 10Mhz clock, generated from 100Mhz clock, shall start at the rising edge of 124Hz clock
- Altera_Forum
Why do you need this clock? what is the ultimate aim? a clock on its own is no use to anyone. What is the system doing?
- Altera_Forum
then what shall i do to solve the problem?
- Altera_Forum
you cant synchronise a clock to two completly unreleated clocks. You may be able to synchronise it every few thousand clocks. But generating clocks with logic is NOT a good idea.
- Altera_Forum
i am beginner in VHDL...kindly elaborate...my requirement is to generate a clock synchronised with two un-synchronised clocks
- Altera_Forum
you cant. Why do you need them synchronised? are you trying to send data across the boundary? why not use a DC fifo?
- Altera_Forum
yes because both are from separate sources...then how to generate a new clock synchronised with these two
- Altera_Forum
you cant syncrhonise 100Mhz and 124 Mhz.
