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Altera_Forum
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13 years ago

VHDL Help

Please help me to generate a clock in VHDL synchronised with rising edges of two external clocks. External clocks are: 100Mhz and 124 Hz Clock to be generated: 10MHz The 10MHz clock is to be g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Actually i need to generate a clock for a sensor....i chose 100Mhz crystal for generating this clock on my pcb...but there is an external clock 124 Hz coming to the pcb and this 10Mhz clock, generated from 100Mhz clock, shall start at the rising edge of 124Hz clock