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Honored Contributor
Honored ContributorVHDL Help
Please help me to generate a clock in VHDL synchronised with rising edges of two external clocks. External clocks are: 100Mhz and 124 Hz Clock to be generated: 10MHz The 10MHz clock is to be g...
Altera_ForumHonored Contributor
Honored Contributoryou cant synchronise a clock to two completly unreleated clocks. You may be able to synchronise it every few thousand clocks. But generating clocks with logic is NOT a good idea.
