VHDL gcd program

HI,

I written vhdl gcd program when i compile it gives an error.

simulator : open source ghdl simulator

command used : ghdl -a gcd.vhd

library IEEE;

use IEEE.STD_Logic_1164.all;

entity gt is

generic (width: natural);

port(clock,reset,load:in std_logic;

a,b : in std_logic_vector(width-1 downto 0);

done : out std_logic;

y : out std_logic_vector(width-1 downto 0)

);

end gt;

architecture RTL of gt is

signal A_New, A_Hold, B_Hold : std_logic_vector(width-1 downto 0);

signal A_less_B : std_logic;

begin

Load:process(clk)

begin

if rising_edge(clk)then

if(Reset='0')then

A_Hold <= A_Hold;

B_Hold <= B_Hold;

else if(load = '1')then

A_Hold <= a;

B_Hold <= b;

else if(A_less_B='1')then

A_Hold <=B_Hold;

B_Hold <=A_New;

else

A_Hold <=A_New;

end if;

end if;

end process Load;

begin

sub:process(A_Hold,B_Hold)

begin

if(A_Hold>=B_Hold)then

A_lessthan_B <= '0';

A_New <=A_Hold - B_Hold;

else

A_lessthan_B <= '1';

A_New <= A_Hold;

end if;

end process sub;

out:process(A_Hold,B_Hold)

begin

if(B_Hold=(others =>'0'))then

Done <='1';

y <=A_Hold;

else

Done <='0';

y <=(others =>'0')

end if;

end process out;

end RTL;