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Altera_Forum
Honored Contributor
14 years agoVHDL gcd program
HI, I written vhdl gcd program when i compile it gives an error. simulator : open source ghdl simulator command used : ghdl -a gcd.vhd library IEEE; use IEEE.STD_Logic_1164.all; ...
Altera_Forum
Honored Contributor
14 years agoWhat errors do you get? I see two potential problems:
if(A_Hold>=B_Hold)thenYou can't directly compare std_logic_vectors. I recommend to use the ieee.numeric_std library and the unsigned/signed types. Then you can directly use the comparison operator.if(B_Hold=(others =>'0'))thenfilling an array with "others" only work in an assignment, and when the destination has a know size. You can't use it for a comparison either. But if B_Hold is an unsigned/signed then you can compare it with an integer instead:if(B_Hold=0)then