Forum Discussion
New ContributorVHDL Counter
Not a fan of schematic design, I always recommend users to use verilog or VHDL to design their project.
Anyhow, you might need to alter a bit of the vhdl template by removing the min_count and max_count. And define the range in the vhdl design.
So that when you convert it into the bdf, it will shown as q[7..0] instead of q[mincount...maxcount]. I guess bdf only recognize it when it is in number.
Took some time to figure it out and attached here a working design with range 40 to 140 so you can check it out.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
New ContributorHi, I've started today in this community.
I see your question as a good example project for our students. We've been systematically implementing counters using VHDL for many years for our CSD course at DIGSYS. Browse our P7 projects on standard synchronous registers and counters.
To invent your 7-bit binary counter modulo 128, we will name it Counter_mod128, we have several options:
- We can chain two universal 4-bit binary counters components that we name Counter_mod16 using terminal counts and count enable control signals. This is what we call our "plan C2". This is multiple file VHDL project.
- We can invent it as FSM using arithmetic libraries and defining state signals STD_LOGIC_vectors. This is what we call our "plan Y" for large binary counters. This project is a single VHDL file, because even if the FSM has a hierarchy of internal processes or components we place them all as processes in the same VHDL file.
We can adjust the final state count as you say in the range from 40 to 50 using counter truncation techniques. We explain truncation and expansion concepts in this lecture L7.3.
regards,
Francesc J. Robert
