VHDL Counter

Not a fan of schematic design, I always recommend users to use verilog or VHDL to design their project.

Anyhow, you might need to alter a bit of the vhdl template by removing the min_count and max_count. And define the range in the vhdl design.

So that when you convert it into the bdf, it will shown as q[7..0] instead of q[mincount...maxcount]. I guess bdf only recognize it when it is in number.

Took some time to figure it out and attached here a working design with range 40 to 140 so you can check it out.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.