Forum Discussion
New ContributorVHDL Counter
Not a fan of schematic design, I always recommend users to use verilog or VHDL to design their project.
Anyhow, you might need to alter a bit of the vhdl template by removing the min_count and max_count. And define the range in the vhdl design.
So that when you convert it into the bdf, it will shown as q[7..0] instead of q[mincount...maxcount]. I guess bdf only recognize it when it is in number.
Took some time to figure it out and attached here a working design with range 40 to 140 so you can check it out.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Super ContributorI believe I have help you on a similar question:
https://community.intel.com/t5/Programmable-Devices/VHDL-logical-block/m-p/1428085#M87663
You can get the up-down counter design in the same way:
- You may use the Counter VHDL template provided in the Quartus tool itself. Insert template> VHDL > Full Design > Arithmetic > Counter > Binary Up/Down Counter.
- Change the MIN_COUNT and MAX_COUNT to your desired range, and you should be able to set the counter range.
Is the design template not working as you intended?
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.
New ContributorHi,
