Forum Discussion
Altera_Forum
Honored Contributor
16 years ago[vhdl] artificial neural network
Hello,
I'm interested in neural networks currently :) I've written some basic ANN implementation in java with ADELINE neurons. (Actually, this is only the background of the problem) I'd like to write a simple neuron in vhdl. input vector is multiplied by weigths, result is sum. If result is > 0 then output = -1 else output = 1 And here comes the problem, I have to multiply input values by weights which are real values. I know that vhdl supports real variables but how should I use it?:confused: I tried like that but it isn't correct code --- Quote Start --- variable weigth:real; variable tmp:real; weight:=0.1; for i in 0 to inputvector'length - 1 loop tmp:=tmp+(weigth*inputvector(i)); end loop; --- Quote End --- I'd be very gradefull for any help!12 Replies
- Altera_Forum
Honored Contributor
Can Anybody provide me some workable examples of ANN in VHDL (or Verilog) -- and its description if possible, code in c , java, or structural scheme --for exploring the pecularities of its design as the simple code maybe not enough, but the code itself would be also valuable.
- Altera_Forum
Honored Contributor
What are you trying to acheive with VHDL. VHDL has the real type for modelling and simulation only - you cannot synthesise them and put them on hardware/FPGA. you have to use std_logic_vector/unsigned/signed/fixed point. Floating point always has to be represented by vectors. The real type is NOT a vector.
If you are using VHDL solely to produce a model, then it is fine, but if you do not intend to put anything onto and FPGA, Id stick to java.