Forum Discussion
Altera_Forum
Honored Contributor
16 years agoWhat are you trying to acheive with VHDL. VHDL has the real type for modelling and simulation only - you cannot synthesise them and put them on hardware/FPGA. you have to use std_logic_vector/unsigned/signed/fixed point. Floating point always has to be represented by vectors. The real type is NOT a vector.
If you are using VHDL solely to produce a model, then it is fine, but if you do not intend to put anything onto and FPGA, Id stick to java.