VHDL 2008 vs System Verilog

I have been using VHDL 2008 for several months now and like the new features of the language. In particular, I use Active-HDL and the VHDL 2008 language constructs are all fully supported. There is a subset of features supported by Quartus. One of the features not supported by Quartus is the general unconstrained type, although Quartus supports unconstrained arrays. Interestingly enough, many of the features of system verilog have been implemented by Quartus . . . which got me looking into the lanugage. In my career, I have written about 10% Verilog, 90% VHDL. For control engineering, VHDL has worked well, with arithmetic operands and filter implementations, etc. However, System Verilog appears to have many VHDL features, with some very nice "data typing" capabilities borrowed from C, such as struct and union. It appears that struct and union are a tad bit more flexible than the VHDL record type, which is also quite flexible. It is just that System Verilog is "ahead" in synthesis features with Quartus. I am wondering if Altera sees this as a long trajectory for development? i.e. system verilog synthesis being ahead of VHDL 2008?

In short, the VHDL data type "record" is one that I most often, and makes code very readable. The use of the generic data types is one "key" ingredient in selecting language use.

Consider, for example:

type counterType is record

done : std_logic;

enable: std_logic;

reset : std_logic;

end record;

signal counter : counterType;

signal counter2: counterType;

Makes possible writing code like this:

-----------------------*/

FSM: process(all)

begin

if HRST then

state <= S0;

recloser.tries <= 0;

FaultOut <= '0';

counter.reset <= '0';

counter.enable <= '0';

elsif rising_edge(MCLK) then

case state is

when S0 =>

if ENABLE and desatCondition then

if recloser.tries < PARAM_RECLOSER_COUNTS then

state <= S1;

counter.reset <= '1';

recloser.tries <= recloser.tries + 1;

else

state <= FAULT;

counter.reset <= '0';

end if;

elsif ENABLE and refresh then

state <= S0;

counter.reset <= '1';

recloser.tries <= 0;

and alos "clustering" control signals around modules to make them easier to handle, such as:

--/* ----------------------------------------

-- Delay counter between recloser tries

--------------------------------------------*/

U3: entity work.DNCNT_INTEGER(BEH)

generic map (

size => PARAM_RECLOSER_WAIT_COUNTS+1

)

port map (

CLK => MCLK,

HRST => counter.reset,

ENABLE => counter.enable,

CNT_VALUE => PARAM_RECLOSER_WAIT_COUNTS,

FLAG => counter.done

);

Thanks, James