VHDL 2008 vs System Verilog

Is there a point to this post?

From what I have heard, better 2008 support (well, theres not alot at the moment) is coming in Q12.1, with Q12 due to hit around mid 2012, so theres going to be a bit of a wait yet. I also understand that verilog/SV has a much larger user base (all internal altera development is Verilog), hence the much greater support for it.

I dont understand what you mean by your reference to "general unconstrained type"? IIRC, the only unconstrained things that 2008 allows are unconstrained array elements, and unconstrained definitions in a record type.

From the code you posted, I dont see any 2008 features in it. It all looks 1993 compatible (apart from the process(all), which IMO allows for more lazy coding than being a useful feature) )