very noisy outputs on EPM3064

Well, the schematic looks ok, the PCB layout is what I would consider less than optimal.
But it appears you are using a two layer board, so not much flexibility to provide solid power/ground to a TQFP SMT device.

That being said, you still need to provide waveforms for your power rail and the clock input signal.
You don't indicate how the 1KHz clock input is being generated and any noise on it will of course cause false triggering like you see.

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I have my EPM3064A PLCC44 development/test board I did, but I included a three terminal 5V to 3.3V regulator on the board.
Power is supplied by a 5V USB connector (no USB, just power). I do have a bulk 10uF caps on the 3.3V regulator output and input.
My board has a socket for a 4pin DIP oscillator; currently I am using a 50MHz 3.3V CMOS oscillator.

A significant difference however is I used a 4 layer board design, with a full ground plane, and split 3.3V/5V power plane.
Signals are all routed on either top or bottom.

A simple test program I use in the 3064A is a series of binary counters, 54 bits in total, driving some discrete LEDS.
A total of 60 registers and all 64 macrocells are used.
The test code runs just fine at 50MHz; Quartus says the -7 part should run at an Fmax of 68.49MHz.
Output signals are clean and the counters operate reliably.