Verilog

I didn't understand your intention yet. Do you mean to select a single bit? [count:0] is a range rather than a bit. Please clarify also the type of the other involved signals.

Fvm,

You might get a registered mux out of that. Really though I would re-write that as a mux if that was your intent since someone picking up your source file might struggle to figure out what it's supposed to do.

The expression can't result in a valid syntax, I think. The right-hand-side has a variable length, it can't be assigned to a target with (obviously) fixed length. Furthermore variable ranges are not supported. You should think about an iteration, that copies individual bits.