Verilog to VHDL

Can some one tell my what this code is in VHDL?

  always @(posedge vga_clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sync_n <= 0;
      else if (1)
          sync_n <= vga_start ? (vsync_temp ~^ hsync_temp) : sync_n_init;
    end

  process (vga_clk, reset_n)
  begin
    if reset_n = '0' then
      sync_n <= std_logic'('0');
    elsif vga_clk'event and vga_clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        sync_n <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(vga_start) = '1'), (vsync_temp xnor hsync_temp), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(sync_n_init)))));
      end if;
    end if;