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Altera_Forum
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18 years ago

Verilog to VHDL

Can some one tell my what this code is in VHDL? always @(posedge vga_clk or negedge reset_n) begin if (reset_n == 0) sync_n <= 0; else if (1) sync_n <= vga...
Altera_Forum's avatar
Altera_Forum
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18 years ago

The operator ~^ is a XNOR.

vsync_temp ~^ hsync_temp

0 ~^ 0 is 1

0 ~^ 1 is 0

1 ~^ 0 is 0

1 ~^ 1 is 1

depending on vga_start,

if 1 sync_n is set to the result of the xnor ,

if 0 sync_n is set to the value of sync_n_init;

unfortunately i cannot read VHDL, it's too much to type, thats why i do it with verilog