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Altera_Forum
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18 years ago

Verilog to VHDL

Can some one tell my what this code is in VHDL? always @(posedge vga_clk or negedge reset_n) begin if (reset_n == 0) sync_n <= 0; else if (1) sync_n <= vga...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I believe the following example would be equivalent VHDL for your Verilog. The

VHDL you provided appears to be machine generated.

process (reset_n, vga_clk)

begin

if (reset_n = '0') then

sync_n <= '0';

elsif (vga_clk'EVENT and vga_clk = '1') then

if (vga_start = '1') then

sync_n <= vsync_temp xnor hsync_temp;

else

sync_n <= sync_n_init;

end if;

end if;

end process;