verilog test code issue

Question

file://localhost/C:/Documents%20and%20Settings/aabelian/Desktop/altera_sim.JPG Hi to all,

This is my first post. sorry if any thing I am doing wrong.

I am new to verilog but I am long time C user. I tried my first code today.

Using simulator I see delay on output side and clk pulse doesn't work.

I am having hard time to understand what am I doing wrong.

any help will appreciate.

thanks

Andre

module led_test(sw1,led1,clk);

input sw1;

output led1;

output clk;

reg led1,led2,clk;

//

initial

begin

led1 <= 0;

end

always@(sw1 )

begin

# 500 clk = ~clk;

end

always@(sw1 )

begin

if(sw1 == 1)

led1 <= 1;

else

led1 <= 0;

end

endmodule

altera_forum · Answer

No,i suggest you try to understand what verilog is really created for.If you want to create a verilog file for synthesis,do not use initial or such sentence.If you want to write a testbench,refer to the books,and you'll see how you should implement this.

altera_forum · Answer

I am reading and I am trying to understand.  Do you know the reason?  thanks  Andre

altera_forum · Answer

sorry to say you don't understand the difference between code for synthesis and code for testbench,so don't try to write one before you really understand!

altera_forum · Answer

This is your second replay with crap. Stop replaying I do not need your feedback.  thanks

altera_forum · Answer

OK,crap,you don't even want to refer to a book,I promise no one will reply to your question!

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verilog test code issue

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