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Altera_Forum
Honored Contributor
Honored Contributorverilog test code issue
file://localhost/C:/Documents%20and%20Settings/aabelian/Desktop/altera_sim.JPG Hi to all, This is my first post. sorry if any thing I am doing wrong. I am new to verilog but I am long time C ...
Altera_ForumHonored Contributor
Honored ContributorNo,i suggest you try to understand what verilog is really created for.If you want to create a verilog file for synthesis,do not use initial or such sentence.If you want to write a testbench,refer to the books,and you'll see how you should implement this.
