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Altera_Forum
Honored Contributor
17 years agoverilog test code issue
file://localhost/C:/Documents%20and%20Settings/aabelian/Desktop/altera_sim.JPG Hi to all, This is my first post. sorry if any thing I am doing wrong. I am new to verilog but I am long time C ...
Altera_Forum
Honored Contributor
17 years agosorry to say you don't understand the difference between code for synthesis and code for testbench,so don't try to write one before you really understand!