Verilog task driving a bidirectional bus

I'm using SystemVerilog, writing a test bench to test a device that has a bidirectional bus. I have been successful directly writing a sequence of statements that put the data on the bus and pulse the write line. But that is cumbersome to write a lot of data. So I want to use the Verilog task capability. I can't seem to get it to drive the bus at all.

Here is the code simplified:

module test();
  wire  data;  // the bidirectional data bus
  reg wr;  // the write enable line
  logic  send_data; // the register for writing data
  my_device u1(
    .data,
    .wr
    );
  assign data = send_data;
  initial begin
    write_gpbus(8'h08);
  end
  task write_gpbus;
    input reg  data_to_send;
    begin
      send_data = data_to_send;
     # 50ns wr = 1'b1;
     # 50ns wr = 1'b0;
    end
endmodule

When I run this I can see send_data getting the correct value of the parameter passed into the task. But data (the actual bus) is always unknown, never gets a value.

If I were to just write directly to the send_data not using the task (as in the code below), then data does get the value. What am I doing wrong here?

  initial begin
    send_data = 8'h08;
  end