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Altera_Forum's avatar
Altera_Forum
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13 years ago

Verilog task driving a bidirectional bus

I'm using SystemVerilog, writing a test bench to test a device that has a bidirectional bus. I have been successful directly writing a sequence of statements that put the data on the bus and pulse th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Never mind! I had some unfinished faulty logic in my_device that was driving the data bus to the unknown state. After turning that off the task correctly drives the bidirectional bus (at least in the output direction).