Honored ContributorHi All,
In VHDL, we can write same set of logic for multiple states as shown below, when STATE_A | STATE_B => ---- ----- How we write an equivalent logic in Verilog. Please help me. regards, freak
Honored ContributorAccording to the Verilog specification
--- Quote Start --- case_statement ::= case ( expression ) case_item { case_item } endcase |casez ( expression ) case_item { case_item } endcase casex ( expression ) case_item { case_item } endcase case_item ::= expression { , expression } : statement_or_null |default [ : ] statement_or_null --- Quote End ---Honored ContributorInstead of a pipe "or" separated list, it is a comma separated list. My favorite on-line verilog syntax check site is asic-world.
one | two becomes one, two:
