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Altera_Forum
Honored Contributor
Honored ContributorVerilog State Assignment
Hi All, In VHDL, we can write same set of logic for multiple states as shown below, when STATE_A | STATE_B => ---- ----- How we write an equiv...
Altera_ForumHonored Contributor
Honored ContributorInstead of a pipe "or" separated list, it is a comma separated list. My favorite on-line verilog syntax check site is asic-world.
one | two becomes one, two:
