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Altera_Forum
Honored Contributor
Honored ContributorVerilog State Assignment
Hi All, In VHDL, we can write same set of logic for multiple states as shown below, when STATE_A | STATE_B => ---- ----- How we write an equiv...
Altera_ForumHonored Contributor
Honored ContributorAccording to the Verilog specification
--- Quote Start --- case_statement ::= case ( expression ) case_item { case_item } endcase |casez ( expression ) case_item { case_item } endcase casex ( expression ) case_item { case_item } endcase case_item ::= expression { , expression } : statement_or_null |default [ : ] statement_or_null --- Quote End ---
