Verilog NetList Writer in Max+plus II(AND1 - ?)

After compiling project I get Verilog file with *.vo open him and find AND1

code...

AND1 AND1_30 ( N_66, N_67 ); // N_66, N_67 is wire

INV INV_31 ( N_67, B7 ); //

AND1 AND1_32 ( N_69, vcc );//

code...

All other compiler like Xilinx, Actel don't know AND1 and see this like Error.

I change AND1 on "and" but it do not work too.

As I know "and" primitives must look like "and name(out, in1, n2 or more ..."in") in Verilog.

From my side it is look like "and name(out, in1) ".

If I change AND1 on assign out = in1; ... Can this change work?