Altera_Forum
Honored Contributor
16 years agoVerilog Help
Hey Guyz!
I need some help with verilog coding. i got this code off opencore website that teaches us how to code a sd card controller.Below shows 2 of the verilog file. A) spiMaster_defines.v `ifdef SIM_COMPILE `define SD_INIT_START_SEQ_LEN 8'h03 `define MAX_8_BIT 8'h08 `else `define SD_INIT_START_SEQ_LEN 8'ha0 `define MAX_8_BIT 8'hff `endif B) initSD.v `include "spiMaster_defines.v" `CLK_SEQ_CHK_FIN: begin next_txDataWen <= 1'b0; if (loopCnt == `SD_INIT_START_SEQ_LEN) begin NextState_initSDSt <= `CLK_SEQ_WT_DATA_EMPTY; end else begin NextState_initSDSt <= `CLK_SEQ_SEND_FF; end end My question is what is the value of `SD_INIT_START_SEQ_LEN ?? Also what is the verilog code in A trying to do? Hope someone can help me as i really need to understand this. Thank you.