Verilog FSM not working on FPGA

I guess, you got a lot of serious Quartus synthesis warnings with your code. If so, you probably shouldn't ignore them.

You e.g. have a counter in an combinational always block. This can't be expected to ever result in reliable operation.

always @(state)
begin
..
count <= (count + 1'b1);
..
end

A counter may count depending on state machine states and other conditions, but it must be placed in an edge sensitive always block.

P.S:

If the present code seems to give correct results in functional (RTL) simulation, this doesn't mean anything.