Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

verilog error

FATAL_ERROR:Simulator:Fuse.cpp:209:1.128.12.1 - Failed to compile one of the generated C files. Please recompile with -mt off -v 1 switch to identify which design unit failed. Process will terminate. For technical support on this issue, please open a WebCase with this project attached .

Process "Simulate Behavioral Model" failed

i am getting this error durin sumulation of my varilog code.please suggest waht to do next.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    i am doing this code in xilinx 13.1.and the simulator is isim....thanks for responding.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    You should ask on a Xilinx forum then, here we talk about Altera.