Verilog: Concept on Blocking assignment and always

Hi jasonkee111,

sanmao is right about synthesis - these constructs will be recognized as D-flops

However, to directly answer your question, how could the simulation behavior differ depending on which always block executes first after reset:

Your circuit will typically have many always blocks that update on the rising edge of clock. The way event-driven simulators calculate the results for all of these processes, is (with non-blocking assignments) to determine the new values but don't let the new values take effect until a short time in the future.

No matter what order these two block are evaluated, the current instantaneous values of y1 and y2 will be used to determine the future values, and the future values will take effect a short time later.

always @(posedge clk) y1 <= y2;

always @(posedge clk) y2 <= y1;

However if you do this:

always @(posedge clk) y1 = y2;

always @(posedge clk) y2 = y1;

You are immediately, instantaneously updating the variables y1 and y2, you are not waiting for "some time in the future" for the updates to take effect. If the simulator evaluates the first block first, y1 will get y2, and then y2 will get the new value of y1 which is y2 also ! If the simulator evaluates the second block first, y2 will get y1, and then y1 will get the new value of y2 (which is y1).

The whole point of <= is to allow simulators to model many things that "happen at once" and then let the updates take place afterwards, so that order doesn't matter. After all, digital logic is all operating in parallel.

The whole point of = is to allow the user to calculate a value with programming language constructs, in zero time.

Hope this helps too...