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Question:
1. How is the flow for above case in terms of always block and blocking
assignment?
2. if reset = 1, y1=0 and y2=1, isn't it? i don understand the
explaination above. So, Try to explain in details.
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Dear jasonkee111,
when you are talking about the simulation semantics of verilog, your remark is correct. For synthesis however the signal assignments within an
always @(posedge clk or posedge rst)
construct will be synthesized as D type flip-flops. The
if (rst) ... ;
construct within the always will be synthesized as sets or presets of the flipflops. The rest of the code will determine the combinatorial logic at the input of the flip-flops.
As a result of this. The two flip flops will be reset in the beginning at the correct level: y1 = 0 and y2 = 1. After that the two flip-flops will toggle at each positive edge of the clock signal.
When writing this code with blocking or non-blocking statements the two descriptions will have the same behavior.
If you want to have your simulation correspond to the synthesized circuit you could use the non-blocking construct in this case.
Within an always construct blocking and non-blocking constructs could of course have different semantics in the determination of what circuit is being synthesized.
Hope this helps...
Honored Contributor
