Altera_Forum
Honored Contributor
Honored ContributorVDHL / verilog ?
bonjour
I use fo many years AHDL but with quartus 10 I must change. What is the difference between VHDL and Verilog? which is better? thanksForum Discussion
7 Replies
Altera_ForumThat's a dangerous question :o
I also have been using AHDL for a 'long' time. A few years back it looked like Altera was going to switch to VHDL, and I made the jump into VHDL. Some three years later, I'm perfectly happy and enjoy VHDL (everyday). It is a bit verbose, but the strong typing is quite helpful. I adopted a naming convention to mimic the a.b = c.d ; ease of connecting modules in AHDL I recently bought a book on Verilog, but it couldn't impress me, maybe I should buy a better book? Here is a link that touts VHDL as superior to Verilog: http://www.sigasi.com/janhdl (http://www.sigasi.com/janhdl). I'm sure you will get others links to defend the opposite :)- Altera_Forum
AHDL is still supported in Q10.0. A lot of old Altera IP is written in AHDL, so I doubt they will ever truly drop support. The difference is that the simulator is gone and Modelsim is recommended. So for AHDL sims you have to first synthesize through Quartus and write out a VHDL/Verilog netlist for Modelsim(it's a structural netlist that you wouldn't even need to open, so you don't have to learn anything for that.) That being said, it's probably worthwhile to learn VHDL/Verilog. As for the whole debate on which is better, most of it is perception(I've never heard of a design house switching languages because one could do something the other couldn't, or the productivity with one was so much better.) And most of the debate is well beyond what AHDL could ever do, so either way would be good.
VHDL is used by government/military. Historically I found it used in the midwest and Europe while verilog was more on the coasts, but it's a lot more mixed than it used to be. Personally, I started with VHDL and used that for many years. I've since learned Verilog and found myself using that when I have no restrictions because I find it quicker to build something and get it going. VHDL gets me caught in type conversions and stuff like that. (That being said, I am more likely to have a bug in my Verilog...) - Altera_Forum
Its like asking if you should buy apples or oranges. They are two different things at the end of the day and those that like oranges will try and convince you to eat them, while the apple camp will try and make you buy apples. At the end of the day they are both fruit with a juicy centre and plenty of nutrition.
Seriously - if you like C, you're probably better off with verilog, and I think AHDL has more of a Verilogness to it. But personally Im a VHDL man (with almost no verilog experience, but some time ploughing through old AHDL designs and interfacing them to newer VHDL). Toss your coin. - Altera_Forum
I do a lot of cross development using C to verify my designs (faster compiles, better debuggers....) For that reason, I use verilog. Most of the time the conversion between C and verilog is as simple as changing "begin / end" to "{ / }". When I started with FPGAs, I looked at VHDL and decided that life was too short for the extra verbosity.
- Altera_Forum
thank you all
I'll see examples to choose ... I regret that Altera abandons AHDL Salutations Pierre - Altera_Forum
I vote verilogHDL.
coz. I use that. I want more friends. hehe. - Altera_Forum--- Quote Start --- Its like asking if you should buy apples or oranges. They are two different things at the end of the day and those that like oranges will try and convince you to eat them, while the apple camp will try and make you buy apples. At the end of the day they are both fruit with a juicy centre and plenty of nutrition. Seriously - if you like C, you're probably better off with verilog, and I think AHDL has more of a Verilogness to it. But personally Im a VHDL man (with almost no verilog experience, but some time ploughing through old AHDL designs and interfacing them to newer VHDL). Toss your coin. --- Quote End --- Hi Tricky, Seriously, I like your analogy but prefer to think of Shish kebab (VHDL) Vs Tika kebab (verilog). I am however not sure of your newly coined terms verilogness and vhdlness but it makes sense. At least it is a bit of a change from the boring tech posts. Apologies.
