VDHL / verilog ?

That's a dangerous question :o

I also have been using AHDL for a 'long' time. A few years back it looked like Altera was going to switch to VHDL, and I made the jump into VHDL. Some three years later, I'm perfectly happy and enjoy VHDL (everyday). It is a bit verbose, but the strong typing is quite helpful. I adopted a naming convention to mimic the a.b = c.d ; ease of connecting modules in AHDL

I recently bought a book on Verilog, but it couldn't impress me, maybe I should buy a better book?

Here is a link that touts VHDL as superior to Verilog: http://www.sigasi.com/janhdl (http://www.sigasi.com/janhdl). I'm sure you will get others links to defend the opposite :)