VDHL / verilog ?

AHDL is still supported in Q10.0. A lot of old Altera IP is written in AHDL, so I doubt they will ever truly drop support. The difference is that the simulator is gone and Modelsim is recommended. So for AHDL sims you have to first synthesize through Quartus and write out a VHDL/Verilog netlist for Modelsim(it's a structural netlist that you wouldn't even need to open, so you don't have to learn anything for that.) That being said, it's probably worthwhile to learn VHDL/Verilog. As for the whole debate on which is better, most of it is perception(I've never heard of a design house switching languages because one could do something the other couldn't, or the productivity with one was so much better.) And most of the debate is well beyond what AHDL could ever do, so either way would be good.

VHDL is used by government/military. Historically I found it used in the midwest and Europe while verilog was more on the coasts, but it's a lot more mixed than it used to be.

Personally, I started with VHDL and used that for many years. I've since learned Verilog and found myself using that when I have no restrictions because I find it quicker to build something and get it going. VHDL gets me caught in type conversions and stuff like that. (That being said, I am more likely to have a bug in my Verilog...)