VCXO removal in Stratix 10 E/H -tiles

Hi,

I am currently investigating Stratix 10 transceiver capabilities. I have a need to create several Tx clocks that lock to a several recovered Rx clocks but I cannot have external VCXO:s to support this (the HW design is already completed). I have come across a brief description of this being done internally by a fPLL and sigma delta modulation in Stratix V devices. Is this possible for Stratix 10 E-tiles?

I have not managed to find any description of this being done with a Stratix 10. I know it is possible in the Xilinx 7-series through to the Ultrascales as in this application note: https://www.xilinx.com/support/documentation/application_notes/xapp1276-vcxo.pdf

/Jens