New MemberHi,
We are working with the following differential clock input pins:
- CLK_[T,B]_2[A,B]_[0:1] (P/N)
- CLK_[T,B]_3[A,B]_[0:1] (P/N)
Could you please confirm the allowed common-mode voltage range for these differential clock inputs?
Super ContributorHi Jay,
you can refer to datasheet for suitable Vicm range. Most Devkits are biasing AC coupled TDS input to Vccio/2 with 4 resistors 1k - 10k.
Regards Frank
New MemberHi,
Do we need to provide external biasing for these clock inputs? If yes, what should be the required input common-mode voltage?
Thanks
Jay
Regular ContributorHello,
- CLK_[T,B]_2[A,B]_[0:1] (P/N)
- CLK_[T,B]_3[A,B]_[0:1] (P/N)
1. Each pin voltage does not exceed VCCIO voltage. Differential clock Vcm within VCCIO. Operational is guaranteed.
2. If you implement LVDS , the Vcm = 1.2V which exceeds VCCIO. So it will need AC coupling when driving HSIO clock inputs from standard LVDS sources. This will allow Agilex 5 HSIO input biasing to establish a compliant Vcm.
regards,
Farabi
