Vcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0

Hi,   We are working with the following differential clock input pins:   - CLK_[T,B]_2[A,B]_[0:1] (P/N) - CLK_[T,B]_3[A,B]_[0:1] (P/N)   Could you please confirm the allowed common-mode voltag...