Vcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0

Hello, 

- CLK_[T,B]_2[A,B]_[0:1] (P/N)

- CLK_[T,B]_3[A,B]_[0:1] (P/N)

1. Each pin voltage does not exceed VCCIO voltage. Differential clock Vcm within VCCIO. Operational is guaranteed. 

2. If you implement LVDS , the Vcm = 1.2V which exceeds VCCIO. So it will need AC coupling when driving HSIO clock inputs from standard LVDS sources. This will allow Agilex 5 HSIO input biasing to establish a compliant Vcm. 

regards,
Farabi