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jaykrishna1's avatar
jaykrishna1
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1 month ago

Vcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0

Hi,   We are working with the following differential clock input pins:   - CLK_[T,B]_2[A,B]_[0:1] (P/N) - CLK_[T,B]_3[A,B]_[0:1] (P/N)   Could you please confirm the allowed common-mode voltag...
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jaykrishna1's avatar
jaykrishna1
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1 month ago

Hi,

Do we need to provide external biasing for these clock inputs? If yes, what should be the required input common-mode voltage?

Thanks

Jay 

Farabi's avatar
Farabi
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1 month ago

Thanks Frank !

 

regards,
Farabi