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arno_va's avatar
arno_va
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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Variable transceiver bitrate on a Cyclone V GX FPGA

We're building a custom transceiver application where we only use the transceiver's TX output. The FPGA's reference clock is clocked externally with a fixed 50 MHz clock for clocking the FPGA's trans...
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  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    2 years ago

    This is what feedback that I got from the internal team that I think worth to share with you:


    "If you adjust the REFCLK input to the Tx PLL, you'll maintain lock for some of the time, but the PLL settings may eventually become sub-optimal. Each data rate has a specific set of PLL settings. 600Mbps may not be the same as 1Gbps. One method you can investigate is to generate a MIF file for 600mpbs and another for 1Gbps. if the two are identical, you might be able to adjust the REFCLK input. However, we don't recommend PLL cascading for XCVR interfaces due to jitter concerns caused by core noise. Having said that, 1Gbps is pretty slow so jitter is less critical, it depends on the protocol requirements."


    Regards,

    Aqid


AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


Do you have any more concern on this issue?


arno_va's avatar
arno_va
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Yes, my problem isn't fixed yet. I think transceiver reconfig doesn't satisfy my needs. I really need to be able to dynamically change the bitrate from 600 to 1000 MBps. So the question remains: can this somehow all be done in the fpga (using an additional PLL driving the transceiver's PLL?) or do I need an external PLL/clock synthesizer for this?