Forum Discussion
Variable transceiver bitrate on a Cyclone V GX FPGA
- 2 years ago
This is what feedback that I got from the internal team that I think worth to share with you:
"If you adjust the REFCLK input to the Tx PLL, you'll maintain lock for some of the time, but the PLL settings may eventually become sub-optimal. Each data rate has a specific set of PLL settings. 600Mbps may not be the same as 1Gbps. One method you can investigate is to generate a MIF file for 600mpbs and another for 1Gbps. if the two are identical, you might be able to adjust the REFCLK input. However, we don't recommend PLL cascading for XCVR interfaces due to jitter concerns caused by core noise. Having said that, 1Gbps is pretty slow so jitter is less critical, it depends on the protocol requirements."
Regards,
Aqid
Hi,
first step would be to clarify your specification based on Cyclone V GX datasheet.
You talk about transceivers, but they don't support data rate below 600 MBPS. So you either need to switch between regular SERDES and transceivers to cover the speed range. Or use special oversampling solutions.
Also, did you read about PLL reconfiguration?
Yes I'm aware it can't go any lower than 600 MBPs. Most important thing for us now is that it at least can be set anywhere between 600 and 1000 MBPs (with 1MBP increments). Yes I read about PLL reconfiguration, but it's totally unclear to me whether this is possible when used with a transceiver, and if so: how? I couldn't find any documentation, or even better examples on how to accomplish that.