Occasional ContributorVariable transceiver bitrate on a Cyclone V GX FPGA
We're building a custom transceiver application where we only use the transceiver's TX output. The FPGA's reference clock is clocked externally with a fixed 50 MHz clock for clocking the FPGA's transceiver. We need to be able to dynamically change the transceiver's TX bit/clock rate (during run-time, without recompiling) to arbitrary values (to anything between 1-1000 MBps, so we can't use clock-switching). I've read all the relevant documentation I could find but it's unclear to me whether this can be performed completely on-chip using eg. one of the FPGA's PLLs or that is only possible using an external PLL/synthesizer IC which clocks the FPGA's reference clock. If I've understand it correctly you can't use transceiver-reconfigure for this, right?
Any help or pointers are highly appreciated.
This is what feedback that I got from the internal team that I think worth to share with you:
"If you adjust the REFCLK input to the Tx PLL, you'll maintain lock for some of the time, but the PLL settings may eventually become sub-optimal. Each data rate has a specific set of PLL settings. 600Mbps may not be the same as 1Gbps. One method you can investigate is to generate a MIF file for 600mpbs and another for 1Gbps. if the two are identical, you might be able to adjust the REFCLK input. However, we don't recommend PLL cascading for XCVR interfaces due to jitter concerns caused by core noise. Having said that, 1Gbps is pretty slow so jitter is less critical, it depends on the protocol requirements."
Regards,
Aqid
