Variable Frequency of clk

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Using a divided clock is usually unsuitable, particularly because crossing timing domains can cause timing violations. But if all design logic, except for the clock divider, is run at the divided frequency, in other words, no signal is crossing the timing domains, the analysis is trivial.

You may want to start with the classical timing analyser and specify the input frequency to the clock divider. As long as there are no external inputs or outputs, that need to be constrained, this should be sufficient.

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http://ifile.it/konx0eg/icao_fpga.schdoc

You can check my design to creat pulse using MAX7000S... Thanks so much